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saiece41Study Group
saiece41
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
12 years 7 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang

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jjvrajaStudent
Anna University, Coimbatore
jjvraja
ISJGP
2010
13 years 8 months ago
On the Hardware Implementation Cost of Crypto-Processors Architectures
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
Nicolas Sklavos
CCCG
2009
14 years 16 days ago
Data Structures for Reporting Extension Violations in a Query Range
Design Rule Checking (DRC) in VLSI design involves checking if a given VLSI layout satisfies a given set of rules, and reporting the violations if any. We propose data structures ...
Ananda Swarup Das, Prosenjit Gupta, Kannan Srinath...
DAC
1998
ACM
14 years 3 months ago
Rate Optimal VLSI Design from Data Flow Graph
This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We ...
Moonwook Oh, Soonhoi Ha