Realizable Reduction for Electromagnetically Coupled RLMC Interconnects

This paper presents a realizable RLMC1 reduction algorithm for extracted interconnect circuits based on two effective approaches: RL branch reduction and RC/LC node reduction. Our algorithm takes advantage of some structures existing extensively in interconnect circuits and hence has extremely fast execution time. It takes about 8 seconds to reduce a circuit of over 300,000 elements while maintaining 3% error and 75% element reduction ratio.

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Rong Jiang, Charlie Chung-Ping Chen
• Keywords: DATE 2004, Extracted Interconnect Circuits, Hardware, Interconnect Circuits, RLMC1 Reduction Algorithm