Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS

Transistor aging effects (NBTI and PBTI) impact the reliability of SRAM in nano-scale CMOS technologies. In this research, the combined effect of NBTI and PBTI on power gated SRAM is analyzed. Optimal source biasing in the standby mode is presented as an effective method for guard-banding against the aging effects. The simulations results in a predictive 32nm technology shows

• Type: Conference
• Year: 2010
• Where: GLVLSI
• Authors: Anuj Pushkarna, Hamid Mahmoodi
• Keywords: GLVLSI 2010, Nano-scale Cmos Technologies, Power Gated Sram, Transistor Aging Effects, VLSI