Scale in Chip Interconnect requires Network Technology

— Continued scaling of CMOS has lead to a problem of scale as gates are faster than light travelling across a chip. Scalability used to be the hallmark of CMOS. Half the size, double the speed, half the power etc.. Today, transistors can leak as much current as they drive, and wires are no longer ”thin film technology” approximated by plate capacitance over ground. Today wires are much thicker than wide and have significantly more capacitance (-coupling) with their neighbors than over ground. A ”short” wire (from one gate to a neighboring one) can be a stub of a few 100nm, while a long wire can connect an IP block with a processor one centimeter away. That is a factor of 100000, which represents a problem of scale and requires fundamentally different solutions. Scalability can be addressed by scaling existing techniques, while problems of scale require new approaches. We discuss problems of scale in the context of chip interconnect.

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: Enno Wein
• Keywords: Chip Interconnect, Hardware, ICCD 2006, Plate Capacitance, Today Wires