Scan-Based BIST Diagnosis Using an Embedded Processor

For system-on-chip designs that contain an embedded processor, this paper present a software based diagnosis scheme that can make use of the processor to aid in diagnosis in a scan-based built-in self-test (BIST) environment. The diagnosis scheme can be used to determine both the scan cells that capture errors as well as the failing test vectors during a BIST session thereby allowing a faster and more precise diagnosis. The BIST session needs to be run only once for diagnosis. The scheme is based on pseudo-random linear compaction of the output response bits. The proposed scheme uses word based linear operations that can be implemented very fast and efficiently on the embedded processor. Experimental results indicate that the proposed scheme is very powerful in identifying the failing test vectors and performs better than previous methods both in terms of the suspect set size and the accuracy of diagnosis.

• Type: Conference
• Year: 2003
• Where: DFT
• Authors: Kedarnath J. Balakrishnan, Nur A. Touba
• Keywords: BIST Session, DFT 2003, Diagnosis Scheme, Embedded Processor, Hardware