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25

DAC
2003
ACM

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Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

15 years 1 months ago

Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL

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John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay

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DAC 2003 | Design Automation | Multiplier Clock Generator |

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Added	13 Nov 2009
Updated	13 Nov 2009
Type	Conference
Year	2003
Where	DAC
Authors	John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas

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