A Self-Reconfigurable Implementation of the JPEG Encoder

Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a JPEG Encoder which exploits this feature. We propose a mixed HW/SW architecture, where most computeintensive components of the application are mapped to application-specific HW cores. These cores dynamically alternate on the FPGA. Our purpose is to describe a realworld application of reconfigurable computing, illustrating how this approach allows for saving area with negligible performance overhead. We built a fully-working prototype, which demonstrates that the reconfigurable JPEG encoder

• Type: Conference
• Year: 2007
• Where: ASAP
• Authors: Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto
• Keywords: Application-specific Hw Cores, ASAP 2007, Hardware, Jpeg Encoder, Reconfigurable Jpeg Encoder