Simultaneous functional-unit binding and floorplanning

As device feature size decreases, interconnection delay becomes the dominating factor of system performance. Thus it is important that accurate physical information is used during high level synthesis. In this paper, we consider the problem of simultaneously performing functional-unit binding and oorplanning. Experimental results indicate that our approach to combine binding and oorplanning is superior to the traditional approach of separating the two tasks.

• Type: Conference
• Year: 1994
• Where: ICCAD
• Authors: Yung-Ming Fang, D. F. Wong
• Keywords: Accurate Physical Information, Device Feature Size, Hardware, ICCAD 1994, Interconnection Delay