Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits

A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with the designer determining when the search is stopped. Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems.

• Type: Conference
• Year: 1994
• Where: DAC
• Authors: Sharad Mehrotra, Paul D. Franzon, Wentai Liu
• Keywords: CMOS VLSI Circuits, Computer Architecture, DAC 1994, Skew Minimization Problems, Stochastic Global Optimization