CMOS VLSI circuits | Sciweavers

31

DAC
1994
ACM

120views Computer Architecture» more DAC 1994»

Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits

14 years 4 months ago

A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with ...

Sharad Mehrotra, Paul D. Franzon, Wentai Liu

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45

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ISLPED
1999
ACM

177views Hardware» more ISLPED 1999»

Low power synthesis of dual threshold voltage CMOS VLSI circuits

14 years 4 months ago

Download www.cecs.uci.edu

The use of dual threshold voltages can signiﬁcantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...

Vijay Sundararajan, Keshab K. Parhi

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40

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DAC
1999
ACM

149views Computer Architecture» more DAC 1999»

Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages

14 years 4 months ago

Download www.cecs.uci.edu

Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...

Vijay Sundararajan, Keshab K. Parhi

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