Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability

14 years 4 months ago

In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free

Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng

Multi-level Asynchronous Circuits | VLSI | VLSID 1995 |

claim paper

Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	VLSID
Authors	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng

Comments (0)