Test cost reduction for SOCs using virtual TAMs and lagrange multipliers

Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically run at lower frequencies (10-50 MHz). The use of high-speed ATE channels to drive slower scan chains leads to an underutilization of resources, thereby resulting in an increase in testing time. We present a new technique to reduce the testing time and test cost by matching highspeed ATE channels to slower scan chains using the concept of virtual test access mechanisms (TAMs). We also present a new TAM optimization framework based on Lagrange multipliers. Experimental results are presented for three industrial circuits from the ITC'02 SOC test benchmarks. Categories and Subject Descriptors B.7.3 [Integrated circuits]: Reliability and testing General Terms Algorithms, Design Keywords Automatic test equipment (ATE), bandwidth matching, scan chains, system-on-chip (SOC), test access mechanism (TAM)

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty
• Keywords: Automatic Test Equipment, DAC 2003, Design Automation, Slower Scan Chains, SOC Test Benchmarks