Test Pattern Generator for Delay Faults

A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this register depends on doubling its length (fig. 3). Test pairs are only generating a half of chosen outputs of the MISR register. Doubling the MISR register makes possible to generate all possible test pairs, which was proved in the article [2, 3, 4]. The disadvantage of this result is too large number of clock cycles. Test pairs for the delay faults consists of a quite number of don't cares. This enables for a considerable reduction of test pairs. Minimizing the number of test pairs means smaller number of clock cycles with a very high coverage factor of test pairs. The process of merging test pairs is shown in the example. These modification result in only one number of programming words and in consequences enable to produce the generator of test pairs without ROM. Experimental results, in which the metho...

• Type: Conference
• Year: 2007
• Where: DDECS
• Authors: Tomasz Rudnicki, Andrzej Hlawiczka
• Keywords: DDECS 2007, Hardware, MISR Register, Possible Test Pairs, Test Pairs