DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
—A Low noise and low power CMOS Image Sensor (CIS) with pixel-level Correlated Double Sampling (CDS) is proposed. As the pixel readout circuit using source follower is major read...
DDECS
2007
IEEE
14 years 20 days ago
2007
IEEE
— From an assumed property, which constrains the inputs of a design under test, we produce a RTL synthesizable design that generates compliant sequences of values for all the sig...
DDECS
2007
IEEE
14 years 2 months ago
2007
IEEE
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
DDECS
2007
IEEE
14 years 5 months ago
2007
IEEE
— The paper describes pre-integrated subsystem consisting of a configurable 8-bit microcontroller and an Internet connection solution. The latter integrates Ethernet Media Access...
DDECS
2007
IEEE
14 years 5 months ago
2007
IEEE
—Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case stu...
DDECS
2007
IEEE
14 years 5 months ago
2007
IEEE
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
DDECS
2007
IEEE
14 years 5 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
DDECS
2007
IEEE
14 years 5 months ago
2007
IEEE
— To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scal...
DDECS
2007
IEEE
14 years 5 months ago
2007
IEEE
Abstract: High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result...
DDECS
2007
IEEE
14 years 5 months ago
2007
IEEE
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...