Test session oriented built-in self-testable data path synthesis

Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of large design space, which may result in a local optimum. In this paper, we present a method which aims to address the problem. Our method tries to find an optimal register assignment for each k-test session. Therefore, it offers a range of designs to the designer with different figures of merit in area and test time. Experimental results show that our method performs better than or comparable to existing BIST synthesis systems.

• Type: Conference
• Year: 1998
• Where: ITC
• Authors: Han Bin Kim, Takeshi Takahashi, Dong Sam Ha
• Keywords: BIST Synthesis, BIST Synthesis Methods, Hardware, ITC 1998, Test Time