Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's

The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. In usual SRAM-based FPGAs, Configurable Interface Modules (CIMs) can be found between the global interconnect and inputs of the logic cells (Input CIMs) or between output of the logic cells and the global interconnect (Output CIMs). It is demonstrated that an input CIM that connects N in segments to a logic cell input requires N in test configurations and that an output CIM that connects a logic cell output to N out segments requires 2 test configurations. Then, it is proven that a set of K in input CIMs can be tested in parallel making the number of required test configurations equal to N in . In the same way, a set of K out output CIMs is shown to require only 2 test configurations if N out > K out . Finally, it is shown that the complete mXm array of logic cells with K in input CIMs and K ...

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
• Keywords: DATE 1999, Hardware, Input Cims, Logic Cells, Output Cims