Timing yield estimation using statistical static timing analysis

—As process variations become a significant problem in deep sub-micron technology, a shift from deterministic static timing analysis to statistical static timing analysis for high-performance circuit designs could reduce the excessive conservatism that is built into current timing design method. In this paper, we address the timing yield problem for sequential circuits and propose a statistical approach to handle it. In our approach, we consider the spatial and path reconvergence correlations between path delays, set-up time and hold time constraints, as well as clock skew due to process variations. We propose a method to get the timing yield based on the delay distributions of register-to-register paths in the circuit. On average, the timing yield results obtained by our

• Type: Conference
• Year: 2005
• Where: ISCAS
• Authors: Min Pan, Chris C. N. Chu, Hai Zhou
• Keywords: ISCAS 2005, Static Timing Analysis, Statistical Static Timing Analysis, Timing Yield