On Using Efficient Test Sequences for BIST

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.

• Type: Conference
• Year: 2002
• Where: VTS
• Authors: René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
• Keywords: On-chip Test Generation, Random Single Input, Test Vector Generation, VLSI, VTS 2002