Sciweavers

203
Voted
EURODAC
1994
IEEE
377views VHDL» more  EURODAC 1994»
15 years 7 months ago
VHDL switch level fault simulation
Christopher A. Ryan, Joseph G. Tront
168
Voted
EURODAC
1994
IEEE
272views VHDL» more  EURODAC 1994»
15 years 7 months ago
A transformation for integrating VHDL behavioral specification with synthesis and software generation
Frank Vahid, Daniel D. Gajski, Sanjiv Narayan
145
Voted
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 6 months ago
System-Level Modeling and Verification: a Comprehensive Design Methodology
Paolo Camurati, Fulvio Corno, Paolo Prinetto, Cath...
142
Voted
EURODAC
1994
IEEE
149views VHDL» more  EURODAC 1994»
15 years 6 months ago
A flexible access control mechanism for CAD frameworks
A. J. van der Hoeven, K. Olav ten Bosch, Rene van ...
140
Voted
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
15 years 7 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
VHDL
Top of PageReset Settings