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204
Voted
EURODAC
1994
IEEE
377views VHDL» more  EURODAC 1994»
15 years 7 months ago
VHDL switch level fault simulation
Christopher A. Ryan, Joseph G. Tront
168
Voted
EURODAC
1994
IEEE
272views VHDL» more  EURODAC 1994»
15 years 7 months ago
A transformation for integrating VHDL behavioral specification with synthesis and software generation
Frank Vahid, Daniel D. Gajski, Sanjiv Narayan
145
Voted
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 6 months ago
System-Level Modeling and Verification: a Comprehensive Design Methodology
Paolo Camurati, Fulvio Corno, Paolo Prinetto, Cath...
142
Voted
EURODAC
1994
IEEE
149views VHDL» more  EURODAC 1994»
15 years 6 months ago
A flexible access control mechanism for CAD frameworks
A. J. van der Hoeven, K. Olav ten Bosch, Rene van ...
140
Voted
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 7 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
VHDL
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