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    VLSID
    1994
    IEEE
    108views VLSI» more  VLSID 1994»
    A New Genetic Algorithm for the Channel Routing Problem
    14 years 1 months ago
    A New Genetic Algorithm for the Channel Routing Problem
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    Jens Lienig, Krishnaiyan Thulasiraman
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    VLSID
    1994
    IEEE
    151views VLSI» more  VLSID 1994»
    A CORDIC Based Programmable DXT Processor Array
    14 years 1 months ago
    A CORDIC Based Programmable DXT Processor Array
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    A CORDIC based processor array which can be programmed by switch settings to compute the Discrete Hariley, Cosine or Sine lhnsforms or their inverses is described. Through a novel...
    V. K. Anuradha, V. Visvanathan
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    VLSID
    1994
    IEEE
    103views VLSI» more  VLSID 1994»
    GLOVE: A Graph-Based Layout Verifier
    14 years 1 months ago
    GLOVE: A Graph-Based Layout Verifier
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    Cyrus Bamji, Jonathan Allen
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    DFT
    1994
    IEEE
    121views VLSI» more  DFT 1994»
    Reconfiguration in 3D Meshes
    14 years 1 months ago
    Reconfiguration in 3D Meshes
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    The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
    Anuj Chandra, Rami G. Melhem
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    VLSID
    1994
    IEEE
    124views VLSI» more  VLSID 1994»
    ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
    14 years 1 months ago
    ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis
    Download  www.cs.kent.edu
    In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
    Samit Chaudhuri, Robert A. Walker
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