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» : Designing a Scalable Build Process
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DAC
2005
ACM
13 years 11 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark
COORDINATION
2009
Springer
14 years 9 months ago
Multicore Scheduling for Lightweight Communicating Processes
Process-oriented programming is a design methodology in which software applications are constructed from communicating concurrent processes. A process-oriented design is typically ...
Carl G. Ritson, Adam T. Sampson, Fred R. M. Barnes
ISCAS
2006
IEEE
87views Hardware» more  ISCAS 2006»
14 years 3 months ago
NoC monitoring: impact on the design flow
Abstract— Networks-on-chip (NoCs) are a scalable interconnect solution to large scale multiprocessor systems on chip and are rapidly becoming reality. As the ratio of embedded co...
Calin Ciordas, Kees Goossens, Andrei Radulescu, Tw...
ASAP
2007
IEEE
175views Hardware» more  ASAP 2007»
13 years 10 months ago
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur S...
HPDC
2010
IEEE
13 years 10 months ago
DiscFinder: a data-intensive scalable cluster finder for astrophysics
DiscFinder is a scalable approach for identifying large-scale astronomical structures, such as galaxy clusters, in massive observation and simulation astrophysics datasets. It is ...
Bin Fu, Kai Ren, Julio López, Eugene Fink, ...