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ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
14 years 1 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
DAC
2009
ACM
14 years 11 days ago
Non-cycle-accurate sequential equivalence checking
We present a novel technique for Sequential Equivalence Checking (SEC) between non-cycle-accurate designs. The problem is routinely encountered in verifying the correctness of a s...
Pankaj Chauhan, Deepak Goyal, Gagan Hasteer, Anmol...
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
EUROMICRO
2006
IEEE
14 years 1 months ago
A Modeling Paradigm for Integrated Modular Avionics Design
This paper presents the modeling paradigm for Integrated Modular Avionics Design MIMAD V0, which is an extensible component-oriented framework that enables high level models of sy...
Abdoulaye Gamatié, Christian Brunette, Roma...
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 8 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...