306 search results - page 31 / 62 » A 3d-audio reconfigurable processor |
DFT
2009
IEEE
14 years 3 months ago
2009
IEEE
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
PARELEC
2000
IEEE
14 years 1 months ago
2000
IEEE
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
DFT
1994
IEEE
14 years 1 months ago
1994
IEEE
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
FPL
2007
Springer
14 years 3 months ago
2007
Springer
In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, avail...