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MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
13 years 11 months ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
14 years 28 days ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
CGO
2010
IEEE
14 years 2 months ago
Level by level: making flow- and context-sensitive pointer analysis scalable for millions of lines of code
We present a practical and scalable method for flow- and contextsensitive (FSCS) pointer analysis for C programs. Our method analyzes the pointers in a program level by level in ...
Hongtao Yu, Jingling Xue, Wei Huo, Xiaobing Feng 0...
OOPSLA
2009
Springer
14 years 1 months ago
Debug all your code: portable mixed-environment debugging
Programmers build large-scale systems with multiple languages to reuse legacy code and leverage languages best suited to their problems. For instance, the same program may use Jav...
Byeongcheol Lee, Martin Hirzel, Robert Grimm, Kath...
CODES
2007
IEEE
14 years 1 months ago
Thread warping: a framework for dynamic synthesis of thread accelerators
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
Greg Stitt, Frank Vahid