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APCSAC
2004
IEEE
13 years 11 months ago
Dynamic Reallocation of Functional Units in Superscalar Processors
In the context of general-purpose processing, an increasing number of diverse functional units are added to cover a wide spectrum of applications. However, it is still possible to ...
Marc Epalza, Paolo Ienne, Daniel Mlynek
ERSA
2006
105views Hardware» more  ERSA 2006»
13 years 8 months ago
A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture
In a coarse-grained reconfigurable architecture, the functions of resources such as Arithmetic Logic Units (ALUs) can be reconfigured. Unlike the programmability of a general purp...
Yuanqing Guo, Cornelis Hoede, Gerard J. M. Smit
CC
2007
Springer
14 years 1 months ago
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors
To achieve high resource utilization for multi-issue Digital Signal Processors (DSPs), production compilers commonly include variants of the iterative modulo scheduling algorithm. ...
Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung...
CF
2004
ACM
14 years 24 days ago
The happy marriage of architecture and application in next-generation reconfigurable systems
New applications and standards are first conceived only for functional correctness and without concerns for the target architecture. The next challenge is to map them onto an arch...
Ingrid Verbauwhede, Patrick Schaumont
FPL
2006
Springer
95views Hardware» more  FPL 2006»
13 years 11 months ago
Automation of IP Core Interface Generation for Reconfigurable Computing
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper ...
Zhi Guo, Abhishek Mitra, Walid A. Najjar