Automation of IP Core Interface Generation for Reconfigurable Computing

Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper we describe a technique that automates the generation of IP core interfaces allowing these to be used as C functions transparently from within C source codes using a reconfigurable computing compiler. We also show how this same tool can be used to support run-time reconfiguration on FPGAs by generating a common wrapper that interfaces to multiple cores.

• Type: Conference
• Year: 2006
• Where: FPL
• Authors: Zhi Guo, Abhishek Mitra, Walid A. Najjar
• Keywords: FPL 2006, Hardware, IP Core, Pre-designed IP Cores, Reconfigurable Computing Compiler