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116
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DATE
2004
IEEE
135views Hardware» more  DATE 2004»
15 years 7 months ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
151
Voted
EMSOFT
2005
Springer
15 years 9 months ago
A sink-n-hoist framework for leakage power reduction
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts have tried to integrate architecture...
Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee
111
Voted
SPAA
2009
ACM
16 years 28 days ago
Optimizing transactions for captured memory
In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is...
Aleksandar Dragojevic, Yang Ni, Ali-Reza Adl-Tabat...
132
Voted
CODES
2005
IEEE
15 years 9 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
120
Voted
DAGSTUHL
2004
15 years 5 months ago
Removing Cycles in Esterel Programs
Abstract. Synchronous programs may contain cyclic signal interdependencies. This prohibits a static scheduling, which limits the choice of available compilation techniques for such...
Jan Lukoschus, Reinhard von Hanxleden