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115
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MICRO
1996
IEEE
106views Hardware» more  MICRO 1996»
15 years 7 months ago
Optimization of Machine Descriptions for Efficient Use
A machine description facility allows compiler writers to specify machine execution constraints to the optimization and scheduling phases of an instruction-level parallelism (ILP)...
John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna...
CASES
2008
ACM
15 years 5 months ago
SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip
fficient Programming Abstractions for Heterogeneous Multicore Systems on Chip Alastair D. Reid Krisztian Flautner Edmund Grimley-Evans ARM Ltd Yuan Lin University of Michigan The ...
Alastair D. Reid, Krisztián Flautner, Edmun...
100
Voted
WOTUG
2008
15 years 5 months ago
Experiments in Translating CSP || B to Handel-C
Abstract. This paper considers the issues involved in translating specifications described in the CSP B formal method into Handel-C. There have previously been approaches to transl...
Steve Schneider, Helen Treharne, Alistair McEwan, ...
DAC
2006
ACM
15 years 9 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
139
Voted
ARCS
1997
Springer
15 years 7 months ago
Compiler Technology for Two Novel Computer Architectures
Before it can achieve wide acceptance, parallelcomputation must be made significantlyeasier to program. One ain obstacles to this goal is the current usage of memory, both abstra...
Ronald Moore, Bernd Klauer, Klaus Waldschmidt