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» A C to Hardware Software Compiler
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CASES
2008
ACM
14 years 15 hour ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
ASM
2008
ASM
14 years 21 hour ago
Using EventB to Create a Virtual Machine Instruction Set Architecture
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine...
Stephen Wright
DAC
2010
ACM
14 years 1 months ago
Processor virtualization and split compilation for heterogeneous multicore embedded systems
Complex embedded systems have always been heterogeneous multicore systems. Because of the tight constraints on power, performance and cost, this situation is not likely to change a...
Albert Cohen, Erven Rohou
CODES
2005
IEEE
14 years 3 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
CASES
2007
ACM
14 years 2 months ago
Scratch-pad memory allocation without compiler support for java applications
ABSTRACT This paper presents the first scratch-pad memory allocation scheme that requires no compiler support for interpreted-language based applications. A scratch-pad memory (SPM...
Nghi Nguyen, Angel Dominguez, Rajeev Barua