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MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
14 years 3 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 11 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
ASPLOS
2009
ACM
14 years 9 months ago
Maximum benefit from a minimal HTM
A minimal, bounded hardware transactional memory implementation significantly improves synchronization performance when used in an operating system kernel. We add HTM to Linux 2.4...
Owen S. Hofmann, Christopher J. Rossbach, Emmett W...
SIGMOD
2008
ACM
190views Database» more  SIGMOD 2008»
14 years 8 months ago
OLTP through the looking glass, and what we found there
Online Transaction Processing (OLTP) databases include a suite of features -- disk-resident B-trees and heap files, locking-based concurrency control, support for multi-threading ...
Stavros Harizopoulos, Daniel J. Abadi, Samuel Madd...
ASPLOS
2010
ACM
14 years 3 months ago
Speculative parallelization using software multi-threaded transactions
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B....