Speculative parallelization using software multi-threaded transactions

With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades. While many scientific programs can be parallelized without speculative techniques, speculative parallelism appears to be the key to continuing this trend for general-purpose applications. Recently-proposed code parallelization techniques, such as those by Bridges et al. and by Thies et al., demonstrate scalable performance on multiple cores by using speculation to divide code into atomic units (transactions) that span multiple threads in order to expose data parallelism. Unfortunately, most software and hardware Thread-Level Speculation (TLS) memory systems and transactional memories are not sufficient because they only support single-threaded atomic units. Multi-threaded Transactions (MTXs) address this problem, but they require expensive hardware support as currently proposed in the literature. This pap...

• Type: Conference
• Year: 2010
• Where: ASPLOS
• Authors: Arun Raman, Hanjun Kim, Thomas R. Mason, Thomas B. Jablin, David I. August
• Keywords: ASPLOS 2010, Atomic Units, Performance, Programming Languages, Thread-level Speculation