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ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 5 months ago
Formal model of data reuse analysis for hierarchical memory organizations
– In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhan...
Ilie I. Luican, Hongwei Zhu, Florin Balasa
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
14 years 11 days ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
SIGMETRICS
1992
ACM
128views Hardware» more  SIGMETRICS 1992»
14 years 21 days ago
MemSpy: Analyzing Memory System Bottlenecks in Programs
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
Margaret Martonosi, Anoop Gupta, Thomas E. Anderso...
ICCD
2006
IEEE
94views Hardware» more  ICCD 2006»
14 years 5 months ago
Reliability Support for On-Chip Memories Using Networks-on-Chip
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...
Federico Angiolini, David Atienza, Srinivasan Mura...
ICCD
2008
IEEE
116views Hardware» more  ICCD 2008»
14 years 5 months ago
Prototyping a hybrid main memory using a virtual machine monitor
— We use a novel virtualization-based approach for computer architecture performance analysis. We present a case study analyzing a hypothetical hybrid main memory, which consists...
Dong Ye, Aravind Pavuluri, Carl A. Waldspurger, Br...