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ARITH
1993
IEEE
14 years 22 days ago
An accurate LNS arithmetic unit using interleaved memory function interpolator
This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage...
David M. Lewis
IPPS
2006
IEEE
14 years 2 months ago
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
Currently run-time reconfigurable hardware offers really attractive features for embedded systems, such as flexibility, reusability, high performance and, in some cases, low-power...
Elena Perez Ramo, Javier Resano, Daniel Mozos, Fra...
CASES
2007
ACM
14 years 18 days ago
Scratch-pad memory allocation without compiler support for java applications
ABSTRACT This paper presents the first scratch-pad memory allocation scheme that requires no compiler support for interpreted-language based applications. A scratch-pad memory (SPM...
Nghi Nguyen, Angel Dominguez, Rajeev Barua
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
14 years 24 days ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
14 years 1 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...