Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
We present a domain-specific approach to representing datapaths for hardware implementations of linear signal transform algorithms. We extend the tensor structure for describing l...
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...
Peter Feldmann, Soroush Abbaspour, Debjit Sinha, G...
Many computational tools have recently begun to benefit from the use of the symmetry inherent in the tasks they solve, and use general-purpose graph symmetry tools to uncover this...
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...