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» A Combined Virtual Shared Memory and Network which Schedules
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CODES
2005
IEEE
14 years 1 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...
ADHOCNETS
2009
Springer
13 years 10 months ago
Efficient Distribution of Large Files in UMTS Supported by Network Coded M2M Data Transfer with Multiple Generations
This paper is a sequel of previous work, in which we have studied the traffic management problem in UMTS. The main objective was to improve the spectral efficiency of cellular netw...
Larissa Popova, Wolfgang H. Gerstacker, Wolfgang K...
DAGSTUHL
2004
13 years 9 months ago
SHIM: A Language for Hardware/Software Integration
Virtually every system designed today is an amalgam of hardware and software. Unfortunately, software and circuits that communicate across the hardware/software boundary are tedio...
Stephen A. Edwards
CICC
2011
106views more  CICC 2011»
12 years 7 months ago
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Efforts to achieve the long-standing dream of realizing scalable learning algorithms for networks of spiking neurons in silicon have been hampered by (a) the limited scalability of...
Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D....
ISCA
2008
IEEE
114views Hardware» more  ISCA 2008»
14 years 2 months ago
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
Jae W. Lee, Man Cheuk Ng, Krste Asanovic