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» A Component Architecture for FPGA-Based, DSP System Design
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ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
14 years 1 months ago
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems
The goal of the research is twofold First, the derivation of a design methodology for FIR filters implementation based on Residue Number System (RNS), aiming at power, delay and h...
Dimitrios Soudris, K. Sgouropoulos, Konstantinos T...
ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
14 years 1 months ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
13 years 8 days ago
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level
— The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, tha...
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Pa...
IESS
2009
Springer
131views Hardware» more  IESS 2009»
14 years 1 months ago
A Hybrid Hardware and Software Component Architecture for Embedded System Design
Abstract. Embedded systems are increasing in complexity, while several metrics such as time-to-market, reliability, safety and performance should be considered during the design of...
Hugo Marcondes, Antônio Augusto Fröhlic...
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
14 years 3 days ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...