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» A Concurrent Model for Linear Logic
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ITC
2003
IEEE
141views Hardware» more  ITC 2003»
14 years 2 months ago
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
Kartik Mohanram, Nur A. Touba
FMSD
2002
81views more  FMSD 2002»
13 years 8 months ago
A Notation and Logic for Mobile Computing
Abstract. We de ne a concurrent mobile system as one where independently executing components may migrate through some space during the course of the computation, and where the pat...
Gruia-Catalin Roman, Peter J. McCann
POPL
2009
ACM
14 years 9 months ago
The theory of deadlock avoidance via discrete control
Deadlock in multithreaded programs is an increasingly important problem as ubiquitous multicore architectures force parallelization upon an ever wider range of software. This pape...
Manjunath Kudlur, Scott A. Mahlke, Stéphane...
APSEC
2002
IEEE
14 years 1 months ago
A Predictive Performance Model to Evaluate the Contention Cost in Application Servers
In multi-tier enterprise systems, application servers are key components to implement business logic and provide services. To support a large number of simultaneous accesses from ...
Shiping Chen, Ian Gorton
EVOW
1999
Springer
14 years 1 months ago
Evolution of Digital Filters Using a Gate Array Model
The traditional paradigm for digital filter design is based on the concept of a linear difference equation with the output response being a weighted sum of signal samples with usua...
Julian F. Miller