36 search results - page 4 / 8 » A Congestion Driven Placement Algorithm for FPGA Synthesis |
FPGA
1995
ACM
14 years 4 days ago
1995
ACM
Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused...
SLIP
2003
ACM
14 years 1 months ago
2003
ACM
In this paper, we describe an accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framew...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
GECCO
2003
Springer
14 years 1 months ago
2003
Springer
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
— This paper presents two contributions. The first is an incremental placement algorithm for placement-aware logic synthesis along with a proof of optimality. The algorithm can ...