36 search results - page 6 / 8 » A Congestion Driven Placement Algorithm for FPGA Synthesis |
GLVLSI
1996
IEEE
14 years 2 months ago
1996
IEEE
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
ISPD
2003
ACM
14 years 3 months ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
DATE
2002
IEEE
14 years 2 months ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...
IPPS
2006
IEEE
14 years 3 months ago
2006
IEEE
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array p...