714 search results - page 126 / 143 » A Decompression Architecture for Low Power Embedded Systems |
DATE
2011
IEEE
12 years 11 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
CHI
2005
ACM
14 years 8 months ago
2005
ACM
Recent years have seen the evolution of networks of tiny low power computing blocks, known as sensor networks. In one class of sensor networks, a non-expert user, who has little o...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
ANSOFT
2002
13 years 7 months ago
2002
Abstract. The real-time process algebra (RTPA) is a set of new mathematical notations for formally describing system architectures, and static and dynamic behaviors. It is recogniz...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to red...