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» A Decompression Architecture for Low Power Embedded Systems
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CSREAESA
2006
13 years 10 months ago
Chip OS: new architecture for next generation embedded system
Nowadays embedded system, hardware/software technology has progressed prosperously. In many field of industrial manufacture and people life, embedded system is indispensable. Rece...
Tianzhou Chen, Yi Lian, Wei Hu
VLSID
2007
IEEE
206views VLSI» more  VLSID 2007»
14 years 9 months ago
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
IJES
2007
79views more  IJES 2007»
13 years 8 months ago
Energy-aware compilation and hardware design for VLIW embedded systems
Abstract: Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption const...
José L. Ayala, Marisa López-Vallejo,...
DAC
1997
ACM
14 years 27 days ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak
HIPEAC
2007
Springer
14 years 2 months ago
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
Major Bhadauria, Sally A. McKee, Karan Singh, Gary...