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» A Decompression Architecture for Low Power Embedded Systems
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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 3 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ISCAS
2003
IEEE
156views Hardware» more  ISCAS 2003»
14 years 2 months ago
GNOMES: a testbed for low power heterogeneous wireless sensor networks
Continuing trends in sensor, semiconductor and communication systems technology (smaller, faster, cheaper) make feasible very dense networks of fixed and mobile wireless devices ...
Erik Welsh, Walt Fish, J. Patrick Frantz
ICCD
2001
IEEE
106views Hardware» more  ICCD 2001»
14 years 5 months ago
A Low-Power Cache Design for CalmRISCTM-Based Systems
Lowering power consumption in microprocessors, whether used in portables or not, has now become one of the most critical design concerns. On-chip cache memories tend to occupy dom...
Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woo...
ISVLSI
2006
IEEE
150views VLSI» more  ISVLSI 2006»
14 years 2 months ago
Design and Analysis of a Low Power VLIW DSP Core
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
Chan-Hao Chang, Diana Marculescu
NOMS
2006
IEEE
14 years 2 months ago
System Support for Management of Networked Low-Power Sensors
— This paper addresses the problem of managing a wireless sensor network with mobile managers. The mobile managers should be able to create their connectivity to the nodes they m...
Jai-Jin Lim, Daniel L. Kiskis, Kang G. Shin