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» A Design Method for Heterogeneous Adders
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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
14 years 1 months ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
14 years 1 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
ARITH
1993
IEEE
14 years 6 days ago
Fast implementations of RSA cryptography
We detail and analyse the critical techniques which may be combined in the design of fast hardware for RSA cryptography: chinese remainders, star chains, Hensel's odd divisio...
Mark Shand, Jean Vuillemin
CAISE
1999
Springer
14 years 11 days ago
Designing the Global Data Warehouse with SPJ Views
Abstract. A global Data warehouse (DW) integrates data from multiple distributed heterogeneous databases and other information sources. DW can be abstractly seen as a set of materi...
Dimitri Theodoratos, Spyros Ligoudistianos, Timos ...
FPL
2006
Springer
113views Hardware» more  FPL 2006»
13 years 11 months ago
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
Alastair M. Smith, George A. Constantinides, Peter...