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FPL
2007
Springer
120views Hardware» more  FPL 2007»
14 years 1 months ago
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
Yohei Hasegawa, Hideharu Amano
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 1 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 12 days ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
FPL
2008
Springer
122views Hardware» more  FPL 2008»
13 years 9 months ago
Mining Association Rules with systolic trees
Association Rules Mining (ARM) algorithms are designed to find sets of frequently occurring items in large databases. ARM applications have found their way into a variety of field...
Song Sun, Joseph Zambreno
FCCM
2004
IEEE
143views VLSI» more  FCCM 2004»
13 years 11 months ago
Reconfigurable Molecular Dynamics Simulator
Current high-performance applications are typically implemented on large-scale general-purpose distributed or multiprocessing systems often based on commodity microprocessors. Fie...
Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha...