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» A Design and Test Technique for Embedded Software
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ITC
1997
IEEE
129views Hardware» more  ITC 1997»
14 years 1 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
DATE
2006
IEEE
113views Hardware» more  DATE 2006»
14 years 3 months ago
Automatic ADL-based operand isolation for embedded processors
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
Anupam Chattopadhyay, B. Geukes, David Kammler, Er...
CASES
2004
ACM
14 years 2 months ago
Memory overflow protection for embedded systems using run-time checks, reuse and compression
Title of thesis: MEMORY OVERFLOW PROTECTION FOR EMBEDDED SYSTEMS USING RUN-TIME CHECKS, REUSE AND COMPRESSION Surupa Biswas, Master of Science, 2004 Thesis directed by: Assistant ...
Surupa Biswas, Matthew Simpson, Rajeev Barua
CODES
2006
IEEE
14 years 3 months ago
Multi-processor system design with ESPAM
For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by emb...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere
LCTRTS
2007
Springer
14 years 3 months ago
External memory page remapping for embedded multimedia systems
As memory speeds and bus capacitances continue to rise, external memory bus power will make up an increasing portion of the total system power budget for system-on-a-chip embedded...
Ke Ning, David R. Kaeli