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ISCAS
2005
IEEE
190views Hardware» more  ISCAS 2005»
14 years 2 months ago
A complete receiver solution for a chaotic direct-sequence spread spectrum communication system
— This paper is devoted to receiver design in a Chaotic Direct-Sequence Spread Spectrum (CD3S) digital communication system. The demodulation is achieved through chaos synchroniz...
M. B. Luca, S. Azou, G. Burel, A. Serbanescu
TSD
2001
Springer
14 years 1 months ago
Determining User Interface Semantics Using Communicating Agents
The Internet offers remote access to many information systems to users independent of time and location. This paper describes an agent based approach to deal with issues that rise ...
L. Ton, Léon J. M. Rothkrantz
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
14 years 2 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
ICCAD
2001
IEEE
91views Hardware» more  ICCAD 2001»
14 years 6 months ago
A System for Synthesizing Optimized FPGA Hardware from MATLAB
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
Malay Haldar, Anshuman Nayak, Alok N. Choudhary, P...
MJ
2006
145views more  MJ 2006»
13 years 9 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...