162 search results - page 10 / 33 » A Distributed Cache Coherence Protocol for Hypercube Multipr... |
ICDCS
1999
IEEE
14 years 21 days ago
1999
IEEE
This work studies the interaction of Web proxy cache coherency and replacement policies using trace-driven simulations. We specifically examine the relative importance of each typ...
ISCA
1995
IEEE
13 years 12 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
EUROPAR
1997
Springer
14 years 17 days ago
1997
Springer
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
TPDS
2008
13 years 7 months ago
2008
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...