110 search results - page 9 / 22 » A Dynamic Fault-Tolerant Mesh Architecture |
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
MOBIHOC
2003
ACM
14 years 26 days ago
2003
ACM
Reliable storage of data with concurrent read/write accesses (or query/update) is an ever recurring issue in distributed settings. In mobile ad hoc networks, the problem becomes e...
GLVLSI
2003
IEEE
14 years 27 days ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...