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» A Dynamic Multithreading Processor
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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
14 years 3 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
HPCA
2005
IEEE
14 years 2 months ago
Chip Multithreading: Opportunities and Challenges
Chip Multi-Threaded (CMT) processors provide support for many simultaneous hardware threads of execution in various ways, including Simultaneous Multithreading (SMT) and Chip Mult...
Lawrence Spracklen, Santosh G. Abraham
ISCA
1989
IEEE
1033views Hardware» more  ISCA 1989»
14 years 27 days ago
Can Dataflow Subsume von Neumann Computing?
: We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?’’ Starting with a simple, “RISC-like” ins...
Rishiyur S. Nikhil
EUROMICRO
1998
IEEE
14 years 1 months ago
Data Speculative Multithreaded Architecture
In this paper we present a novel processor microarchitecture that relieves three of the most important bottlenecks of superscalar processors: the serialization imposed by true dep...
Pedro Marcuello, Antonio González
HPCA
2008
IEEE
14 years 9 months ago
Runahead Threads to improve SMT performance
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
Tanausú Ramírez, Alex Pajuelo, Olive...