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» A Dynamic Multithreading Processor
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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 5 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 5 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
SOSP
2009
ACM
14 years 5 months ago
The multikernel: a new OS architecture for scalable multicore systems
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
Andrew Baumann, Paul Barham, Pierre-Évarist...
PEPM
2009
ACM
14 years 5 months ago
Self-adjusting computation: (an overview)
Many applications need to respond to incremental modifications to data. Being incremental, such modification often require incremental modifications to the output, making it po...
Umut A. Acar
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
14 years 3 months ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...